The present invention relates to the formation of dielectric layers used in integrated semiconductor circuits. More particularly, the present invention relates to tailoring the shape of a dielectric layer covering a step such as a metal step associated with metalization patterns within integrated semiconductor circuits.
As is more completely explained below prior art processes of depositing dielectric or insulative layers in semiconductor devices initially were accomplished by an RF (radio frequency) sputtering process not involving a bias between the anode and cathode of the sputtering device. Such a process resulted in good conformal step coverage in that the coating thickness covering the sidewall of the metal step was nearly equal to the film thickness covering lateral surfaces.
A disadvantage of this prior art process was cusping or the building up of material at the corner of layers. Further, in Very Large Scale Integration (VLSI) technology, individual metalized circuits are spaced very closely together. If these individual metalizations are covered with conformal dielectric layers covering the sidewall of the metalization with a thickness substantially equal to the film thickness, particularly with cusping at the corners, a topography having a very high aspect ratio of height to width can be created between the conformal coatings of adjacent metalizations. Such a topography is a difficult to fill and often results in void formation during the formation of layers. This void formation will result in device failures due to gas expansion in the voids during subsequent processing steps.
With the improvement of adding a bias between the cathode and the anode in RF sputtering, the process being called RF bias sputtering, cusping was lessened, and dielectric coverage of metalization steps became less conformal. In RF bias sputtering, the bias between the cathode and the anode causes resputtering at the substrate or semiconductor device since the bias accelerates ions into the corners (of what would be conformal coatings) to taper the corners. This helps reduce cusping and the very high aspect ratios between the dielectric elevations above adjacent metalization patterns since the dielectric elevations have sloping edges which are more easily planarized in subsequent or concurrent processing.
A disadvantage, however, of RF bias sputtering as it exists in the prior art is that the tapered corners caused by the ion bombardment tend to have sharp edges at the corners, and these sharp edges are exaggerated as cusps in subsequent layers of metalization and dielectric. This undesirable cusping, while less serious than with unbiased RF sputtering, still presents a significant problem in multilayer devices since each subsequent layer tends to exaggerate the cusp in the previous layer, thus resulting in less planarization than is desired.
Through the present invention, the shape of a dielectric layer covering a step in a semiconductor device can be tailored to round sharp edges or corners, to substantially eliminate cusping, and/or to otherwise improve planarization. Such tailored shapes to dielectric layers were previously unknown.